The present invention relates to computer systems and multiprocessor computer systems. More particularly, the present invention relates to multiprocessor systems which include a cache memory system.
It is well known that cache memories have been highly effective in increasing the throughput of small and large uniprocessor and multiprocessor systems. In multiprocessor systems, cache memories are normally configured in either of two ways. The first is a shared cache configuration in which a cache memory is utilized for one or several main memory modules. It is accessible by all of the processors within the system. The second configuration is a private cache arrangement in which the cache memory is dedicated to a single processor. These configurations are described in an article titled "Effects of Cache Coherency in Multiprocessors" by Michael Dubois and Fay A. Briggs, IEEE Transactions on Computers, Volume C-31, No. 11, November, 1982.
Additionally, multiprocessor systems have been configured to share a common control unit which includes a cache memory. U.S. Pat. Nos. 4,378,591 and 4,392,200 are examples of these types of systems. In such systems, the processing units connect to a common bus and include arbitration circuits for allocating available bus cycles for accessing the cache memory. It has been found that considerable time is expended in resolving access conflicts among processors. This in turn reduces system performance, in addition to adding to the complexity of the system.
Additionally, in the system disclosed in U.S. Pat. No. 4,378,591 other sources of requests for bus cycles, such as a first in first out (FIFO) memory are included within the cache subsystem. This resource must be granted access to the cache memory via the local bus on a priority basis. The FIFO is granted a higher priority than the processing units, so that information transfers which are commonly main memory write operations would take precedence. That is, the cache update operations are assigned a higher priority than the processor requests which further slow down the performance of the system.
One prior art uniprocessor system utilizes a memory system which contains a cache and main memory implemented by fully segmented pipelines. The system is a single personal computer and as such can only accommodate a single user system. For a discussion of the system, reference may be made to the article entitled "The Memory System of a High-Performance Personal Computer" by Douglas W. Clark, Butler W. Lampson and Kenneth A. Pier, IEEE Transactions on Computers, Volume C-30, No. 10, October, 1981.
Accordingly, it is a primary object of the present invention to provide a high performance cache system which is able to handle requests from a plurality of sources.
It is a further object of the present invention to provide a system which permits independently operating sources to share a cache unit on a conflict-free basis.